Electronic equipment, an example of which is a computer, generally uses a printed circuit board for the purpose of wiring various elements. In a printed circuit board, a wiring pattern is formed on an insulating substrate formed generally of a polyimide such that a conducting layer is formed by sputtering or plating and the layer is etched thereafter. It is required that information processing apparatuses today provide a high density of mounted elements in order to satisfy a need for smaller and faster operating apparatuses. As a result, wiring patterns formed on printed circuit boards today have a very fine and concentrated pattern. In an apparatus required to perform especially fast operations, such as a supercomputer, a multi-layer circuit board is employed for the purpose of minimizing length of wires in a wiring pattern.
Forming a fine wiring pattern on a circuit board is liable to produce errors during exposure process or during etching process, thus necessitating an introduction of technique for trimming a wiring pattern on a circuit board. In order to improve yield of the production process, circuit board trimming technique is essential with circuit boards produced through a large number of processes, such as multi-layer circuit boards having a high density of mounted elements and used in supercomputers and the like.
FIG. 1 and FIGS. 2(A), 2(B) show an example of multi-layer circuit board. FIG. 1 is a perspective view of the circuit board and FIGS. 2(A) and 2(B) are cross-sections.
Referring to FIG. 1, the multi-layer circuit board comprises: a polyimide layer 10 formed on a ceramic substrate (not shown in the figure) by spin coating means; and a first wiring pattern 11a formed on the polyimide layer 10. As shown in the cross-section of FIG. 2(A), the wiring pattern 11a is embedded in a first polyimide interlayer dielectric 11b. The layer 10, the wiring pattern 11a and the interlayer dielectric 11b constitute a first-layer structure 11 of the circuit board.
A second wiring pattern 12a is formed on the upper main surface of the interlayer dielectric 11b; a second interlayer dielectric 12b is formed so that the second wiring pattern 12a is embedded therein. Thus, the second-layer structure 12 of the circuit board is formed. As shown in FIG. 2(A), a viahole 13.sub.1 is provided in the interlayer dielectric 11b so as to connect the first wiring pattern 11a and the second wiring pattern 12a. A viahole 13.sub.2 is provided in the second interlayer dielectric 12b so that the second wiring pattern and a third wiring pattern formed on the interlayer dielectric 12b are electrically connected via the viahole 13.sub.12.
Since the interlayer dielectrics 11b and 12b are very thin (20-50 .mu.m), a defect, such as a pinhole as indicated by a numeral 15 in FIG. 2(B), could cause the otherwise coated wiring pattern to be exposed. When a conducting layer is formed on the interlayer dielectric 12b so as to form the wiring pattern 14 thereon, the pinhole 15 becomes embedded in the conducting layer, possibly causing the wiring pattern 14 formed on the upper main surface of the interlayer dielectric 12b and the second wiring pattern 12 to be short-circuited. The likelihood of a short circuit becomes particularly great in a circuit board used in high-speed electronic devices, since spacings provided in a wiring pattern therein are small. In such a device, a minor error in an exposure process or etching process might even lead to a short-circuited wiring pattern in a layer.
In order to improve yield in producing circuit boards and in order to lower the cost of electronic apparatuses, a technique is required for trimming a circuit board where a short circuit as described above is created. FIGS. 3(A), 3(B), FIGS. 4(A), 4(B) and FIGS. 5(A), 5(B) show examples of trimming a wiring pattern on a circuit board. FIGS. 3(A) and (B) show an example of how an interlayer short circuit is trimmed; FIGS. 4(A) and 4(B) show an example of how an intra-layer short circuit is trimmed; and FIGS. 5(A) and 5(B) show an example of trimming a wiring pattern provided to penetrate a multi-layer circuit board in such a manner that the pattern is clear of a power source pattern. In the case of the example shown in FIGS. 3(A) and 3(B), the wiring pattern 12a short-circuited due to the pinhole 15 shown in FIG. 3(A) is trimmed by detaching the part in contact with the pinhole 15 from the other parts, as shown in FIG. 3(B). In the case shown in FIGS. 4(A) and 4(B), a short-circuited part 16a shown in FIG. 4(A) is trimmed by being cut out as shown in FIG. 4(B). In the case shown in FIGS. 5(A) and 5(B), a short-circuited part 12x between a pattern 12a', provided to penetrate the layers constituting a multi-layer circuit board as shown in FIG. 5(A), and a power source pattern 12a, provided to surround the pattern 12a' via the insulating region 12b, is cut and thus removed as shown in FIG. 5(B).
Conventionally, such trimming of a wiring pattern on the circuit board has been carried out manually by an expert. However, a board having highly-concentrated patterns such as the circuit boards used in today's high-speed information processing apparatuses has such a narrow patterning width (20-50 .mu.m) that manual trimming has become almost impossible to perform. Although a method has been proposed for cutting out a defective part by using a high-power laser, such a method is liable to cause a damage to a polyimide insulating coat and is impractical because it requires delicate adjustment of irradiation power.
The Japanese Laid-Open Patent Publication 3-57293 proposes a method of cutting out a defective wiring pattern using an ultrasonic cutter in order to resolve the problem of trimming the circuit board pattern. FIG. 6 shows an example of how a defective pattern is trimmed according to the above-mentioned known art. In the figure, those parts that correspond to those in the figures already explained are given the same reference numerals from figure to figure.
Referring to FIG. 6, the above-mentioned known art uses a cutter 18 having a cutting edge 18c is used to cut out a defective pattern indicated by a numeral 12x. The cutting edge 18c is provided with ultrasonic oscillation by an excitation part 18a via an oscillation transmitting part (horn) 18b. The defective pattern 12x is cut and thus removed, by applying the cutting edge 18c to the pattern to be cut, and by moving the circuit board (11+12) in a direction V coinciding with the direction of the ultrasonic oscillation indicated by an arrow in the oscillation transmitting part 18b. Typically, an ultrasonic oscillation having a frequency in the order of several tens of a kHz is supplied to the cutter 18 so as to apply, to the cutting edge thereof, an ultrasonic oscillation having an amplitude of between several microns to several tens of micron.
FIG. 7(A) shows an example of trimming a wiring pattern on a circuit board where an apparatus according to the above-mentioned known art is employed. Referring to FIG. 7(A), the cutting edge 18c of the ultrasonic cutter 18 is lowered below the upper surface of the pattern 12a by a depth Z.sub.1 and the pattern 12a is scraped by the depth Z.sub.1 by moving the circuit board (11+12) in a direction indicated by an arrow V. This process is repeated until the pattern 12a is completely removed. According to the aforementioned known art, the pattern 12a can be removed by a width b corresponding to a width B of the cutting edge 18c, thus greatly improving yield in producing the circuit board.
According to the known method mentioned above, the position of the cutting edge 18c determines the depth of cutting. It is to be noted, however, that warp or irregularity of the dimension of more than 10 .mu.m may exist on the printed circuit board. Such a warp or irregularity causes the relative position of the cutting edge 18c with respect to the board to be altered. When there is a depression on the board, the cutting edge is positioned above the depression so that the pattern 12a can not be cut. On the other other hand, when the cutting edge meets a raised part, it cuts not only the pattern 12a but also the insulating coat 11b of the board. As shown in FIG. 9(A), a depression tends to be formed on the insulating layer 12b immediately above the viahole 13.sub.1. When a defective pattern 14x formed on such a depression is removed by means of an apparatus employing the above-mentioned known art, a problem results that a part of the pattern 14x remains unremoved, while the insulating layer 12b is scraped off to an undesired depth, as shown in FIG. 9(B). This is because the cutting edge 18c of the aforementioned known art can be moved only in the horizontal direction. A repetitive cutting operation for removing the residual of the pattern 14x causes the damage to the board to grow. Such a problem of circuit board damage becomes even more serious with multi-layer circuit board used in high-speed information processing apparatuses such as supercomputers.
It is also to be noted that, in the above-mentioned known art, it is assumed that the pattern is removed with the cutting depth Z.sub.1 by feeding the cutting edge 18c with the cutting depth Z.sub.1, as shown in FIG. 7(A). However, the cutting depth of an ultrasonic cutter varies due to change, through wear, of the state of the cutting edge, the manner in which the exchangeable cutting edge 18c is screwed to the oscillation transmitting part (horn) 18b, variation in the relative position of the cutting edge 18c with respect to the oscillation transmitting part 18b and temperature-induced variation in ultrasonic oscillation transmitted along the cutting edge. It happens, therefore, that, when the cutting depth is small, the pattern is not removed to the desired depth Z.sub.1 even when the cutter is fed to the depth Z.sub.1 in the direction toward the board as shown in FIG. 7(A), resulting in the pattern being removed only by the depth Z.sub.O. In such a case, even after stepwise cutting operations, which feed the cutter below the surface of the board, causes a part of the pattern remains to be cut, as shown in FIG. 7(C). A further stepwise cutting operation intended to reach the desired depth and to prevent any part of the pattern from remaining unremoved, causes the damage to the insulating layer on the board to grow. Although this damage can be reduced by presetting the unit cutting amount Z.sub.1 to be relatively small, such an arrangement causes the number of repetitive operations for removing the whole pattern to increase, thereby requiring a lot of time for a cutting process and reducing throughput of the repair process.
When removing conductor path bridges and normal wiring patterns having a known pattern thickness, the process can be achieved by presetting the unit cutting amount Z.sub.1 such that Z.sub.1 multiplied by the number of repetitive operations exceeds the pattern thickness. However, a defective part created by a short circuit has an unknown thickness and an unknown shape. Accordingly, the above-mentioned known art presets the number of repetitive operations to be five so that a pattern having a maximum thickness as shown in FIG. 8(A) can be cut. However, a more common type of defective part such as the one shown in FIG. 8(B) would require only two repetitive operations. That is, the five repetitive operations as shown in FIG. 8(A) is superfluous because three of the five operations do not make contact and are unnecessary. Generally speaking, it is impossible, by using the above-mentioned known art, to remove a defective pattern formed on a board having a complex surface shape or a defective pattern having a complex shape itself, while the damage to the board can be minimized.